IEEE - Institute of Electrical and Electronics Engineers, Inc. - Clock tree synthesis with data-path sensitivity matching

13th Asia and South Pacific Design Automation Conference ASP-DAC 2008

Author(s): M.R. Guthaus ; D. Sylvester ; R.B. Brown
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2008
Conference Location: Seoul, South Korea
Conference Date: 21 March 2008
Page(s): 498 - 503
ISBN (CD): 978-1-4244-1922-7
ISBN (Paper): 978-1-4244-1921-0
DOI: 10.1109/ASPDAC.2008.4484001
Regular:

This paper investigates methods for minimizing the impact of process variation on clock skew using buffer and wire sizing. While most papers on clock trees ignore data-path circuit variations and... View More

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