IEEE - Institute of Electrical and Electronics Engineers, Inc. - Design rule optimization of regular layout for leakage reduction in nanoscale design

13th Asia and South Pacific Design Automation Conference ASP-DAC 2008

Author(s): A.R. Subramaniam ; R. Singhal ; Chi-Chao Wang ; Yu Cao
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2008
Conference Location: Seoul, South Korea
Conference Date: 21 March 2008
Page(s): 474 - 479
ISBN (CD): 978-1-4244-1922-7
ISBN (Paper): 978-1-4244-1921-0
DOI: 10.1109/ASPDAC.2008.4483997
Regular:

The effect of non-rectilinear gate (NRG) due to sub-wavelength lithograph dramatically increases the leakage current by more than 15X. To mitigate this penalty, we have developed a systematic... View More

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