IEEE - Institute of Electrical and Electronics Engineers, Inc. - Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof

13th Asia and South Pacific Design Automation Conference ASP-DAC 2008

Author(s): U. Krautz ; M. Wedler ; W. Kunz ; K. Weber ; C. Jacobi ; M. Pflanz
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2008
Conference Location: Seoul, South Korea
Conference Date: 21 March 2008
Page(s): 398 - 403
ISBN (CD): 978-1-4244-1922-7
ISBN (Paper): 978-1-4244-1921-0
DOI: 10.1109/ASPDAC.2008.4483983
Regular:

In this paper we describe a practical methodology to formally verify highly optimized, industrial multipliers. We define a multiplier description language which abstracts from low-level... View More

Advertisement