IEEE - Institute of Electrical and Electronics Engineers, Inc. - A capacitive boosted buffer technique for high-speed process-variation-tolerant interconnect in UDVS application

13th Asia and South Pacific Design Automation Conference ASP-DAC 2008

Author(s): Saihua Lin ; Yu Wang ; Rang Luo ; Huazhong Yang
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2008
Conference Location: Seoul, South Korea
Conference Date: 21 March 2008
Page(s): 304 - 309
ISBN (CD): 978-1-4244-1922-7
ISBN (Paper): 978-1-4244-1921-0
DOI: 10.1109/ASPDAC.2008.4483964
Regular:

In this paper, we propose a new capacitive boosted buffer technique that can be used in high speed interconnect for ultra-dynamic voltage scaling (UDVS) application with the process variation... View More

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