IEEE - Institute of Electrical and Electronics Engineers, Inc. - Hierarchical Krylov subspace reduced order modeling of large RLC circuits

13th Asia and South Pacific Design Automation Conference ASP-DAC 2008

Author(s): Duo Li ; D.S.X.-D. Tan
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2008
Conference Location: Seoul, South Korea
Conference Date: 21 March 2008
Page(s): 170 - 175
ISBN (CD): 978-1-4244-1922-7
ISBN (Paper): 978-1-4244-1921-0
DOI: 10.1109/ASPDAC.2008.4483934
Regular:

In this paper, we propose a new model order reduction approach for large interconnect circuits using hierarchical decomposition and Krylov subspace projection-based model order reduction. The new... View More

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