IEEE - Institute of Electrical and Electronics Engineers, Inc. - Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA

13th Asia and South Pacific Design Automation Conference ASP-DAC 2008

Author(s): Cheng-Tao Hsieh ; J. Cong ; Zhiru Zhang ; Shih-Chieh Chang
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2008
Conference Location: Seoul, South Korea
Conference Date: 21 March 2008
Page(s): 10 - 15
ISBN (CD): 978-1-4244-1922-7
ISBN (Paper): 978-1-4244-1921-0
DOI: 10.1109/ASPDAC.2008.4483919
Regular:

In this paper we discuss optimizing the interconnect power of designs implemented in FPGA platforms. In particular, we reduce the glitch power on interconnects associated with the output of... View More

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