IEEE - Institute of Electrical and Electronics Engineers, Inc. - A Tunable Clock Buffer for Intra-die PVT Compensation in Single-Edge Clock (SEC) Distribution Networks

2008 9th International Symposium on Quality Electronic Design (ISQED '08)

Author(s): J. Mueller ; R. Saleh
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 March 2008
Conference Location: San Jose, CA, USA
Conference Date: 17 March 2008
Page(s): 572 - 577
ISBN (Paper): 978-0-7695-3117-5
DOI: 10.1109/ISQED.2008.4479799
Regular:

As processes shrink, the on-chip variability grows and this variation causes clock skew to rapidly consume a larger-and-larger percentage of the clock period. New techniques to reduce skew are... View More

Advertisement