IEEE - Institute of Electrical and Electronics Engineers, Inc. - ILP Based Gate Leakage Optimization Using DKCMOS Library during RTL Synthesis

2008 9th International Symposium on Quality Electronic Design (ISQED '08)

Author(s): S.P. Mohanty
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 March 2008
Conference Location: San Jose, CA, USA
Conference Date: 17 March 2008
Page(s): 174 - 177
ISBN (Paper): 978-0-7695-3117-5
DOI: 10.1109/ISQED.2008.4479721
Regular:

In this paper dual-K (DKCMOS) technology is proposed as a method for gate leakage power reduction. An integer linear programming (ILP) based algorithm is proposed for its optimization during... View More

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