IEEE - Institute of Electrical and Electronics Engineers, Inc. - Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic

2008 9th International Symposium on Quality Electronic Design (ISQED '08)

Author(s): K. Yelamarthi ; Chien-In Henry Chen
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 March 2008
Conference Location: San Jose, CA, USA
Conference Date: 17 March 2008
Page(s): 143 - 147
ISBN (Paper): 978-0-7695-3117-5
DOI: 10.1109/ISQED.2008.4479715
Regular:

A major challenge in the design of microprocessor circuits is transistor sizing in dynamic CMOS logic due to increased number of channel-connected transistors on various paths of the design, and... View More

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