IEEE - Institute of Electrical and Electronics Engineers, Inc. - Soft Error Rate Determination for Nanometer CMOS VLSI Logic

40th Southeastern Symposium on System Theory

Author(s): Fan Wang ; V.D. Agrawal
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 March 2008
Conference Location: New Orleans, LA, USA
Conference Date: 16 March 2008
Page(s): 324 - 328
ISBN (CD): 978-1-4244-1807-7
ISBN (Paper): 978-1-4244-1806-0
ISSN (Paper): 0094-2898
DOI: 10.1109/SSST.2008.4480247
Regular:

Nanometer CMOS VLSI circuits are highly sensitive to soft errors due to environmental causes such as cosmic radiation and charged particles. These phenomena, also known as single-event upset (SEU)... View More

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