IEEE - Institute of Electrical and Electronics Engineers, Inc. - Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs

Design, Automation & Test in Europe. DATE'08

Author(s): S. Bahukudumbi ; K. Chakrabarty ; R. Kacprowicz
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 March 2008
Conference Location: Munich, Germany
Conference Date: 10 March 2008
Page(s): 1,103 - 1,106
ISBN (CD): 978-3-9810801-4-8
ISBN (Paper): 978-3-9810801-3-1
DOI: 10.1109/DATE.2008.4484925
Regular:

Wafer-level test during burn-in (WLTBI) has recently emerged as a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, the testing of multiple cores of a... View More

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