IEEE - Institute of Electrical and Electronics Engineers, Inc. - Performance-Constrained Different Cell Count Minimization for Continuously-Sized Circuits

Design, Automation & Test in Europe. DATE'08

Author(s): H. Yoshida ; M. Fujita
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 March 2008
Conference Location: Munich, Germany
Conference Date: 10 March 2008
Page(s): 1,099 - 1,102
ISBN (CD): 978-3-9810801-4-8
ISBN (Paper): 978-3-9810801-3-1
DOI: 10.1109/DATE.2008.4484924
Regular:

A continuously-sized circuit resulting from transistor sizing consists of gates with large variety of sizes. In this paper, we first provide a formal formulation of performance-constrained... View More

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