IEEE - Institute of Electrical and Electronics Engineers, Inc. - Zero-Efficient Buffer Design for Reliable Network-on-Chip in Tiled Chip-Multi-Processor

Design, Automation & Test in Europe. DATE'08

Author(s): Jun Wang ; Hongbo Zeng ; Kun Huang ; Ge Zhang ; Yan Tang
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 March 2008
Conference Location: Munich, Germany
Conference Date: 10 March 2008
Page(s): 792 - 795
ISBN (CD): 978-3-9810801-4-8
ISBN (Paper): 978-3-9810801-3-1
DOI: 10.1109/DATE.2008.4484913
Regular:

Network-on-chip (NoC) is a promising solution for efficient interconnection between processor cores in chip-multi-processor (CMP). This paper is focusing on the energy-efficient design of... View More

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