IEEE - Institute of Electrical and Electronics Engineers, Inc. - Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network

Design, Automation & Test in Europe. DATE'08

Author(s): Wanping Zhang ; Yi Zhu ; Wenjian Yu ; Ling Zhang ; Rui Shi ; He Peng ; Zhi Zhu ; Lew Chua-Eoan ; R. Murgai ; T. Shibuya ; N. Ito ; Chung-Kuan Cheng
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 March 2008
Conference Location: Munich, Germany
Conference Date: 10 March 2008
Page(s): 537 - 540
ISBN (CD): 978-3-9810801-4-8
ISBN (Paper): 978-3-9810801-3-1
DOI: 10.1109/DATE.2008.4484906
Regular:

This paper proposes an efficient method to find the worst case of voltage violation by multi-domain clock gating in an on-chip power network. We first present a voltage response in an arbitrary... View More

Advertisement