IEEE - Institute of Electrical and Electronics Engineers, Inc. - Effective Loop Partitioning and Scheduling under Memory and Register Dual Constraints

Design, Automation & Test in Europe. DATE'08

Author(s): C.J. Xue ; E.H.-M. Sha ; Meikang Qiu
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 March 2008
Conference Location: Munich, Germany
Conference Date: 10 March 2008
Page(s): 1,202 - 1,207
ISBN (CD): 978-3-9810801-4-8
ISBN (Paper): 978-3-9810801-3-1
DOI: 10.1109/DATE.2008.4484842
Regular:

Loops are the most important sections for embedded applications. To achieve high performance, two loop transformation techniques are often applied, namely loop pipelining and loop partitioning,... View More

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