IEEE - Institute of Electrical and Electronics Engineers, Inc. - Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors

Design, Automation & Test in Europe. DATE'08

Author(s): Sanghyun Park ; A. Shrivastava ; Yunheung Paek
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 March 2008
Conference Location: Munich, Germany
Conference Date: 10 March 2008
Page(s): 1,190 - 1,195
ISBN (CD): 978-3-9810801-4-8
ISBN (Paper): 978-3-9810801-3-1
DOI: 10.1109/DATE.2008.4484840
Regular:

The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-end processors can... View More

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