IEEE - Institute of Electrical and Electronics Engineers, Inc. - Latch Modeling for Statistical Timing Analysis

Design, Automation & Test in Europe. DATE'08

Author(s): S.X. Shi ; A. Ramalingam ; Daifeng Wang ; D.Z. Pan
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 March 2008
Conference Location: Munich, Germany
Conference Date: 10 March 2008
Page(s): 1,136 - 1,141
ISBN (CD): 978-3-9810801-4-8
ISBN (Paper): 978-3-9810801-3-1
DOI: 10.1109/DATE.2008.4484831
Regular:

Latch based circuits are widely adopted in high performance circuits. But there is a lack of accurate latch models for doing timing analysis. In this paper, we propose a new latch delay model in... View More

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