IEEE - Institute of Electrical and Electronics Engineers, Inc. - An Efficient Method for Chip-Level Statistical Capacitance Extraction Considering Process Variations with Spatial Correlation

Design, Automation & Test in Europe. DATE'08

Author(s): Wangyang Zhang ; Wenjian Yu ; Zeyi Wang ; Zhiping Yu ; Rong Jiang ; Jinjun Xiong
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 March 2008
Conference Location: Munich, Germany
Conference Date: 10 March 2008
Page(s): 580 - 585
ISBN (CD): 978-3-9810801-4-8
ISBN (Paper): 978-3-9810801-3-1
DOI: 10.1109/DATE.2008.4484739
Regular:

An efficient method is proposed to consider the process variations with spatial correlation, for chip-level capacitance extraction based on the window technique. In each window, an efficient... View More

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