IEEE - Institute of Electrical and Electronics Engineers, Inc. - Using Reconfigurable Logic to Optimise GPU Memory Accesses

Design, Automation & Test in Europe. DATE'08

Author(s): B. Cope ; P.Y.K. Cheung ; W. Luk
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 March 2008
Conference Location: Munich, Germany
Conference Date: 10 March 2008
Page(s): 44 - 49
ISBN (CD): 978-3-9810801-4-8
ISBN (Paper): 978-3-9810801-3-1
DOI: 10.1109/DATE.2008.4484658
Regular:

Memory access patterns common in video processing algorithms, which are unsuited to the GPU (Graphics Processing Unit) memory system, are identified. We develop REDA (Reconfigurable Engine for... View More

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