IEEE - Institute of Electrical and Electronics Engineers, Inc. - Integrating RTL IPs into TLM Designs Through Automatic Transactor Generation

Design, Automation & Test in Europe. DATE'08

Author(s): N. Bombieri ; N. Deganello ; F. Fummi
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 March 2008
Conference Location: Munich, Germany
Conference Date: 10 March 2008
Page(s): 15 - 20
ISBN (CD): 978-3-9810801-4-8
ISBN (Paper): 978-3-9810801-3-1
DOI: 10.1109/DATE.2008.4484653
Regular:

Transaction Level Modeling (TLM) is an emerging design practice for overcoming increasing design complexity. It aims at simplifying the design flow of embedded systems by designing and verifying a... View More

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