IEEE - Institute of Electrical and Electronics Engineers, Inc. - A Hybrid Interconnect Network-on-Chip and a Transaction Level Modeling Approach for Reconfigurable Computing

2008 4th IEEE International Symposium on Electronic Design, Test and Applications (DELTA '08)

Author(s): T. Lenart ; H. Svensson ; V. Owall
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2008
Conference Location: Hong Kong, China
Conference Date: 23 January 2008
Page(s): 398 - 404
ISBN (Paper): 978-0-7695-3110-6
DOI: 10.1109/DELTA.2008.85
Regular:

This paper presents a hybrid interconnect network consisting of a local network with dedicated wires and a global hierarchical network. A distributed memory approach enables the possibility to use... View More

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