IEEE - Institute of Electrical and Electronics Engineers, Inc. - Design of High-Speed Floating Point Multiplier

2008 4th IEEE International Symposium on Electronic Design, Test and Applications (DELTA '08)

Author(s): S.V. Siddamal ; R.M. Banakar ; B.C. Jinaga
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2008
Conference Location: Hong Kong, China
Conference Date: 23 January 2008
Page(s): 285 - 289
ISBN (Paper): 978-0-7695-3110-6
DOI: 10.1109/DELTA.2008.19
Regular:

Floating-point (FP) multiplication finds application in image and signal processing. This paper presents a hardware implementation of optimized IEEE 754 single precision floating-point multiplier.... View More

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