IEEE - Institute of Electrical and Electronics Engineers, Inc. - Power Attack Resistant Efficient FPGA Architecture for Karatsuba Multiplier

2008 21st International Conference on VLSI Design

Author(s): Chester Rebeiro ; Debdeep Mukhopadhyay
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2008
Conference Location: Hyderabad, India
Conference Date: 4 January 2008
Page(s): 706 - 711
ISBN (Paper): 0-7695-3083-4
ISSN (Electronic): 2380-6923
ISSN (Paper): 1063-9667
DOI: 10.1109/VLSI.2008.65
Regular:

The paper presents an architecture to implement Karatsuba Multiplier on an FPGA platform. Detailed analysis has been carried out on how existing algorithms utilize FPGA resources. Based on the... View More

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