IEEE - Institute of Electrical and Electronics Engineers, Inc. - A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and Shifters

2008 21st International Conference on VLSI Design

Author(s): S. Das ; S.P. Khatri
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2008
Conference Location: Hyderabad, India
Conference Date: 4 January 2008
Page(s): 572 - 579
ISBN (Paper): 0-7695-3083-4
ISSN (Paper): 1063-9667
DOI: 10.1109/VLSI.2008.112
Regular:

In modern digital signal processing (DSP) and graphics applications, the arithmetic sum-of-products, shifters and adders are important modules, contributing a significant amount to the overall... View More

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