IEEE - Institute of Electrical and Electronics Engineers, Inc. - MoCSYS: A Multi-Clock Hybrid Two-Layer Router Architecture and Integrated Topology Synthesis Framework for System-Level Design of FPGA Based On-Chip Networks

2008 21st International Conference on VLSI Design

Author(s): A. Janarthanan ; K.A. Tomko
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2008
Conference Location: Hyderabad, India
Conference Date: 4 January 2008
Page(s): 397 - 402
ISBN (Paper): 0-7695-3083-4
ISSN (Paper): 1063-9667
DOI: 10.1109/VLSI.2008.79
Regular:

Complex system-on-chip designs targeted for FPGAs merit sophisticated communication architectures to support a host of high performance applications. In this research we implement a hybrid... View More

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