IEEE - Institute of Electrical and Electronics Engineers, Inc. - Fast Congestion Aware Routing for Pin Assignment

2008 21st International Conference on VLSI Design

Author(s): S. Prasad
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2008
Conference Location: Hyderabad, India
Conference Date: 4 January 2008
Page(s): 343 - 347
ISBN (Paper): 0-7695-3083-4
ISSN (Paper): 1063-9667
DOI: 10.1109/VLSI.2008.110
Regular:

Macroblock (aka partition) pin assignment and routing are important tasks in typical top-down hierarchical physical design. Routers use pin locations as connection points to route the design with... View More

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