IEEE - Institute of Electrical and Electronics Engineers, Inc. - An Elitist Non-Dominated Sorting Based Genetic Algorithm for Simultaneous Area and Wirelength Minimization in VLSI Floorplanning

2008 21st International Conference on VLSI Design

Author(s): P. Fernando ; S. Katkoori
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2008
Conference Location: Hyderabad, India
Conference Date: 4 January 2008
Page(s): 337 - 342
ISBN (Paper): 0-7695-3083-4
ISSN (Paper): 1063-9667
DOI: 10.1109/VLSI.2008.97
Regular:

VLSI floor-planning in the gigascale era must deal with multiple objectives including wiring congestion, performance and reliability. Genetic algorithms lend themselves naturally to... View More

Advertisement