IEEE - Institute of Electrical and Electronics Engineers, Inc. - A Fast Settling 100dB OPAMP in 180nm CMOS Process with Compensation Based Optimisation

2008 21st International Conference on VLSI Design

Author(s): A.K. Kundu ; S. Chatterjee ; T.K. Bhattacharyya
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2008
Conference Location: Hyderabad, India
Conference Date: 4 January 2008
Page(s): 311 - 316
ISBN (Paper): 0-7695-3083-4
ISSN (Paper): 1063-9667
DOI: 10.1109/VLSI.2008.86
Regular:

A two-stage gain-boosted OPAMP with 100dB DC gain, 807 MHz unity gain bandwidth (UGB) and rail to rail output swing in 180 nm digital CMOS process is presented. A compensation based optimisation... View More

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