IEEE - Institute of Electrical and Electronics Engineers, Inc. - Dynamic Error Detection for Dependable Cache Coherency in Multicore Architectures

2008 21st International Conference on VLSI Design

Author(s): Hui Wang ; S. Baldawa ; R. Sangireddy
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2008
Conference Location: Hyderabad, India
Conference Date: 4 January 2008
Page(s): 279 - 285
ISBN (Paper): 0-7695-3083-4
ISSN (Paper): 1063-9667
DOI: 10.1109/VLSI.2008.68
Regular:

In chip multiprocessor (CMP) systems the various effects of technology scaling make the on chip components more susceptible to faults. Most of the earlier schemes that address fault tolerance... View More

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