IEEE - Institute of Electrical and Electronics Engineers, Inc. - Low power and high speed 8x8 bit multiplier using non-clocked pass transistor logic

2007 International Conference on Intelligent and Advanced Systems

Author(s): C. Senthilpari ; A.K. Singh ; K. Diwakar
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 November 2007
Conference Location: Kuala Lumpur, Malaysia
Conference Date: 25 November 2007
Page(s): 1,374 - 1,378
ISBN (CD): 978-1-4244-1356-0
ISBN (Paper): 978-1-4244-1355-3
DOI: 10.1109/ICIAS.2007.4658609
Regular:

In this paper we have analyzed an 8-bit multiplier circuit using non clocked pass gate families with help of carry save multiplier (CSA) technique. The multiplier cell of the adder is designed by... View More

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