IEEE - Institute of Electrical and Electronics Engineers, Inc. - Bit-serial systolic architecture for 2-D non-separable discrete wavelet transform

2007 International Conference on Intelligent and Advanced Systems

Author(s): B.K. Mohanty ; P.K. Meher
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 November 2007
Conference Location: Kuala Lumpur, Malaysia
Conference Date: 25 November 2007
Page(s): 1,355 - 1,358
ISBN (CD): 978-1-4244-1356-0
ISBN (Paper): 978-1-4244-1355-3
DOI: 10.1109/ICIAS.2007.4658605
Regular:

In this paper, we present a novel fully-pipelined bit-serial architecture for systolic implementation of non-separable two-dimensional discrete wavelet transform (2-D DWT). The computations which... View More

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