IEEE - Institute of Electrical and Electronics Engineers, Inc. - Top Level SOC Interconnectivity Verification Using Formal Techniques

2007 IEEE International Workshop on Microprocessor Test and Verification (MTV)

Author(s): S.K. Roy
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2007
Conference Location: Austin, TX, USA
Conference Date: 5 December 2007
Page(s): 63 - 70
ISBN (Paper): 978-0-7695-3241-7
ISSN (Paper): 1550-4093
DOI: 10.1109/MTV.2007.22
Regular:

SOCs are designed by integrating existing in house cores/intellectual properties (IPs), or third party core/IPs provided by external vendors to reduce design turn-around time and cost. The... View More

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