IEEE - Institute of Electrical and Electronics Engineers, Inc. - A Scalable Symbolic Simulator for Verilog RTL

2007 IEEE International Workshop on Microprocessor Test and Verification (MTV)

Author(s): S. Sunkari ; S. Chakraborty ; V. Vedula ; K. Maneparambil
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2007
Conference Location: Austin, TX, USA
Conference Date: 5 December 2007
Page(s): 51 - 59
ISBN (Paper): 978-0-7695-3241-7
ISSN (Paper): 1550-4093
DOI: 10.1109/MTV.2007.13
Regular:

Symbolic simulation is an important technique used informal property verification and test generation for digital circuits. Existing symbolic simulators predominantly operate at the gate level,... View More

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