IEEE - Institute of Electrical and Electronics Engineers, Inc. - Reduction of Power Dissipation during Scan Testing by Test Vector Ordering

2007 IEEE International Workshop on Microprocessor Test and Verification (MTV)

Author(s): Wang-Dauh Tseng ; Lung-Jen Lee
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2007
Conference Location: Austin, TX, USA
Conference Date: 5 December 2007
Page(s): 15 - 21
ISBN (Paper): 978-0-7695-3241-7
ISSN (Paper): 1550-4093
DOI: 10.1109/MTV.2007.6
Regular:

Test vector ordering is recognized as a simple and non-intrusive approach to assist test power reduction. Simulation based test vector ordering approach to minimize circuit transitions requires... View More

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