IEEE - Institute of Electrical and Electronics Engineers, Inc. - Hybrid resistor/FET-logic demultiplexer architecture design for hybrid CMOS/nanodevice circuits

25th International Conference on Computer Design, ICCD 2007

Author(s): Shu Li ; Tong Zhang
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2007
Conference Location: Lake Tahoe, CA, USA
Conference Date: 7 October 2007
Page(s): 574 - 579
ISBN (CD): 978-1-4244-1258-7
ISBN (Paper): 978-1-4244-1257-0
ISSN (Paper): 1063-6404
DOI: 10.1109/ICCD.2007.4601955
Regular:

Hybrid nanoelectronics are emerging as one viable option to sustain the Moorepsilas Law after the CMOS scaling limit is reached. One main design challenge in hybrid nanoelectronics is the... View More

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