IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 2.5-3.125Gbps clock and data recovery circuit for multi-standard transceivers

2007 International Conference on Microelectronics

Author(s): A. Elshazly ; M. Dessouky ; H.F. Ragai
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2007
Conference Location: Cairo, Egypt
Conference Date: 29 December 2007
Page(s): 295 - 298
ISBN (CD): 978-1-4244-1847-3
ISBN (Paper): 978-1-4244-1846-6
DOI: 10.1109/ICM.2007.4497714
Regular:

This paper describes the design of a 2.5 to 3.2 Gbps clock and data recovery circuit using a second-order analog phase interpolator. The jitter transfer characteristics of the circuit meets jitter... View More

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