IEEE - Institute of Electrical and Electronics Engineers, Inc. - An FPGA implementation of AES with support for counter and feedback modes

2007 International Conference on Microelectronics

Author(s): J.S. Grabowski ; A. Youssef
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2007
Conference Location: Cairo, Egypt
Conference Date: 29 December 2007
Page(s): 39 - 42
ISBN (CD): 978-1-4244-1847-3
ISBN (Paper): 978-1-4244-1846-6
ISSN (Electronic): 2159-1679
ISSN (Paper): 2159-1660
DOI: 10.1109/ICM.2007.4497657
Regular:

The advanced encryption standard (AES) is a symmetric key block cipher that has been approved by NIST as a replacement for the data encryption standard (DES). In this paper, we present an FPGA... View More

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