IEEE - Institute of Electrical and Electronics Engineers, Inc. - A solution for memory collision in semi-parallel FPGA-based LDPC decoder design

2007 41st Asilomar Conference on Signals, Systems and Computers (ACSSC '07)

Author(s): R. Zarubica ; S.G. Wilson
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 November 2007
Conference Location: Pacific Grove, CA, USA
Conference Date: 4 November 2007
Page(s): 982 - 986
ISBN (CD): 978-1-4244-2110-7
ISBN (Paper): 978-1-4244-2109-1
ISSN (Paper): 1058-6393
DOI: 10.1109/ACSSC.2007.4487366
Regular:

Low Density Parity Check (LDPC) decoders implementing long blocklength codes require semi-parallel design. One challenge when implementing these codes on Field Programmable Gate Arrays (FPGAs) is... View More

Advertisement