IEEE - Institute of Electrical and Electronics Engineers, Inc. - A new scheduling algorithm for processor-based logic emulation systems

2007 50th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS '07)

Author(s): A. Yazdanshenas ; M.A.S. Khalid
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 August 2007
Conference Location: Montreal, Que., Canada
Conference Date: 5 August 2007
Page(s): 1,505 - 1,508
ISBN (CD): 978-1-4244-1176-4
ISBN (Paper): 978-1-4244-1175-7
ISSN (Paper): 1548-3746
DOI: 10.1109/MWSCAS.2007.4488826
Regular:

In this paper a design compilation CAD tool suite, that maps gate-level netlists of design-under-test (DUT) into a specific class of processor-based logic emulation systems, is presented. The... View More

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