IEEE - Institute of Electrical and Electronics Engineers, Inc. - Integrated test scheduling, wrapper design, and TAM assignment for hierarchical SOC

2007 50th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS '07)

Author(s): H.M. Harmanani ; R. Farah
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 August 2007
Conference Location: Montreal, Que., Canada
Conference Date: 5 August 2007
Page(s): 1,388 - 1,391
ISBN (CD): 978-1-4244-1176-4
ISBN (Paper): 978-1-4244-1175-7
ISSN (Paper): 1548-3746
DOI: 10.1109/MWSCAS.2007.4488807
Regular:

System-on-chip (SOCs) test minimization has received a lot of attention in the past few years. However, most recent work assumed flat hierarchy. This assumption is unrealistic especially in the... View More

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