IEEE - Institute of Electrical and Electronics Engineers, Inc. - A comparison of ILP based global routing models for VLSI ASIC design

2007 50th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS '07)

Author(s): Zhen Yang ; S. Areibi ; A. Vannelli
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 August 2007
Conference Location: Montreal, Que., Canada
Conference Date: 5 August 2007
Page(s): 1,141 - 1,144
ISBN (CD): 978-1-4244-1176-4
ISBN (Paper): 978-1-4244-1175-7
ISSN (Paper): 1548-3746
DOI: 10.1109/MWSCAS.2007.4488758
Regular:

The sub-micron regime has caused the interconnect delay to become a critical determiner of circuit performance. As a result, circuit layout is starting to play a more important role in today's... View More

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