IEEE - Institute of Electrical and Electronics Engineers, Inc. - Efficient simulation of jitter tolerance for all-digital data recovery circuits

2007 50th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS '07)

Author(s): S.I. Ahmed ; T.A. Kwasniewski
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 August 2007
Conference Location: Montreal, Que., Canada
Conference Date: 5 August 2007
Page(s): 1,070 - 1,073
ISBN (CD): 978-1-4244-1176-4
ISBN (Paper): 978-1-4244-1175-7
ISSN (Paper): 1548-3746
DOI: 10.1109/MWSCAS.2007.4488745
Regular:

Clock and data recovery (CDR) Circuits are being increasingly marketed as intellectual property (IP) blocks for complex system-on-chip (SoC) and network-on-chip (NoC) products. As part of the... View More

Advertisement