IEEE - Institute of Electrical and Electronics Engineers, Inc. - Hardware optimization for a reconfigurable Polyphase-FFT design using common sub-expression elimination

2007 50th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS '07)

Author(s): H. Ho ; V. Szwarc ; T. Kwasniewski
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 August 2007
Conference Location: Montreal, Que., Canada
Conference Date: 5 August 2007
Page(s): 650 - 653
ISBN (CD): 978-1-4244-1176-4
ISBN (Paper): 978-1-4244-1175-7
ISSN (Paper): 1548-3746
DOI: 10.1109/MWSCAS.2007.4488663
Regular:

In this paper, the implementation of a reconfigurable polyphase-FFT circuit and its building blocks designed for low hardware complexity are presented. The polyphase-FFT circuit can be configured... View More

Advertisement