IEEE - Institute of Electrical and Electronics Engineers, Inc. - 3.2-Gb/s 1024-b rate-1/2 LDPC decoder chip using a flooding-type update-schedule algorithm

2007 50th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS '07)

Author(s): N. Onizawa ; T. Ikeda ; T. Hanyu ; V.C. Gaudet
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 August 2007
Conference Location: Montreal, Que., Canada
Conference Date: 5 August 2007
Page(s): 217 - 220
ISBN (CD): 978-1-4244-1176-4
ISBN (Paper): 978-1-4244-1175-7
ISSN (Paper): 1548-3746
DOI: 10.1109/MWSCAS.2007.4488574
Regular:

This paper presents a high-speed low-density parity-check (LDPC) decoder chip using a new decoding algorithm, called a flooding-type update-schedule algorithm. Since node computations are... View More

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