IEEE - Institute of Electrical and Electronics Engineers, Inc. - A tapered partitioning method for “delay energy product” optimization in global interconnects

2007 50th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS '07)

Author(s): M. Mehran ; N. Masoumi
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 August 2007
Conference Location: Montreal, Que., Canada
Conference Date: 5 August 2007
Page(s): 21 - 24
ISBN (CD): 978-1-4244-1176-4
ISBN (Paper): 978-1-4244-1175-7
ISSN (Paper): 1548-3746
DOI: 10.1109/MWSCAS.2007.4488532
Regular:

The delay of global interconnects increases with technology scaling because their thickness to width aspect ratio tend to increase with scaling, while the lengths remain constant or even increase.... View More

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