IEEE - Institute of Electrical and Electronics Engineers, Inc. - Test time minimization for system-on-chip with test bus assignment and sizing

2007 International IEEE Northeast Workshop on Circuits and Systems (NEWCAS '07)

Author(s): H.M. Harmanani ; R. Sawan
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 August 2007
Conference Location: Montreal, Que, Canada
Conference Date: 5 August 2007
Page(s): 1,281 - 1,284
ISBN (CD): 978-1-4244-1164-1
ISBN (Paper): 978-1-4244-1163-4
DOI: 10.1109/NEWCAS.2007.4488014
Regular:

Test access is a major problem in testing embedded cores as it directly impacts testing time and hardware cost. Test access mechanism (TAM) is responsible for test data transport and is... View More

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