IEEE - Institute of Electrical and Electronics Engineers, Inc. - Performance of Parallel Prefix Adders implemented with FPGA technology

2007 International IEEE Northeast Workshop on Circuits and Systems (NEWCAS '07)

Author(s): K. Vitoroulis ; A.J. Al-Khalili
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 August 2007
Conference Location: Montreal, Que, Canada
Conference Date: 5 August 2007
Page(s): 498 - 501
ISBN (CD): 978-1-4244-1164-1
ISBN (Paper): 978-1-4244-1163-4
DOI: 10.1109/NEWCAS.2007.4487969
Regular:

Parallel Prefix Adders have been established as the most efficient circuits for binary addition. Their regular structure and fast performance makes them particularly attractive for VLSI... View More

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