IEEE - Institute of Electrical and Electronics Engineers, Inc. - Optimized realization of large-size two’s complement multipliers on FPGAs

2007 International IEEE Northeast Workshop on Circuits and Systems (NEWCAS '07)

Author(s): Shuli Gao ; D. Al-Khalili ; N. Chabini
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 August 2007
Conference Location: Montreal, Que, Canada
Conference Date: 5 August 2007
Page(s): 494 - 497
ISBN (CD): 978-1-4244-1164-1
ISBN (Paper): 978-1-4244-1163-4
DOI: 10.1109/NEWCAS.2007.4487968
Regular:

This paper presents an optimized design approach of two's complement large-size multipliers using embedded multipliers in FPGAs. The realization is based on Baugh-Wooley's algorithm. To achieve... View More

Advertisement