IEEE - Institute of Electrical and Electronics Engineers, Inc. - A systolic array for sequence comparison based on two-logic-levels processing element

2007 International IEEE Northeast Workshop on Circuits and Systems (NEWCAS '07)

Author(s): N. Hireche ; J.M.P. Langlois ; G. Nicolescu
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 August 2007
Conference Location: Montreal, Que, Canada
Conference Date: 5 August 2007
Page(s): 73 - 76
ISBN (CD): 978-1-4244-1164-1
ISBN (Paper): 978-1-4244-1163-4
DOI: 10.1109/NEWCAS.2007.4487953
Regular:

In this work, we implement a dynamic programming (DP) algorithm for sequence comparison (SC) purposes. We aimed at obtaining a better compromise between the processing acceleration optimization... View More

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