IEEE - Institute of Electrical and Electronics Engineers, Inc. - Impact of process variations on bus-encoding schemes for delay minimization in VLSI interconnects

11th IEEE Workshop on Signal Propagation on Interconnects

Author(s): C. Raghunandan ; K.S. Sainarayanan ; M.B. Srinivas
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 2007
Conference Location: Genova, Italy
Conference Date: 13 May 2007
Page(s): 245 - 248
ISBN (CD): 978-1-4244-1224-2
ISBN (Paper): 978-1-4244-1223-5
DOI: 10.1109/SPI.2007.4512262
Regular:

Process variations can have a significant impact on both device and interconnect performance in deep submicron (DSM) technologies. In this paper, authors discuss the impact of process parameter... View More

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